1. Field of the Invention
The present invention relates to a digital PLL (Phase Lock Loop) circuit and an optical disk apparatus having the digital PLL circuit.
2. Description of the Related Art
In recordable optical disks (e.g. CD-R/RW, DVD+R/RW, and DVD-R/RW), physical address data are embedded beforehand in a meandering groove referred to as a wobble. The wobble is formed in a groove track forming process in which the track is formed in a manner wobbling in a radial direction. The physical address data are expressed in various modulation methods (e.g. frequency modulation used for CD-R/RW, phase modulation used for DVD+R/RW, modulation of discontinuous points of a wobble used for DVD-R/Rw). The carrier frequency of a wobble is set in proportion to the frequency of a reference clock signal for writing (writing reference clock signal).
The writing reference clock signal is generated by a PLL (Phase Lock Loop) circuit, in which the frequency of the wobble signal obtained from the above-described wobble (hereinafter referred to as “wobble frequency”) is used as a comparison frequency. In generating a writing reference clock signal with a PLL circuit having the wobble frequency as the comparative frequency, it is essential to generate a clock signal with steady low jitter.
The PLL is realized by an analog circuit having a VCO (Voltage Controlled Oscillator). Since the free running frequency of the analog VCO tends to change due to changes in atmospheric temperature and power supply voltage, the acquisition time of the PLL circuit tends to become long and its lock tends to dislocate due to disturbance. Therefore, in recent years, there has developed a demand for a digital PLL (DPLL: Digital PLL) that is fully digitized.
For example, a DPLL circuit according to a related art case is provided with an integration circuit for integrating output signals of a phase comparator in which signals output from the integration circuit and the phase comparator are time-divisionally switched and added to a loop filter (for example, see Japanese Laid-Open Patent Application No. 60-245312).
In another exemplary DPLL circuit according to a related art case, after detecting the phase difference between low time resolution oscillation clock signals and desired high time resolution clock signals, the output signals of the digital VCO are phase-modulated based on the phase difference information and are supplied to a frequency band controlling part of the next step so that only the basic frequency components are output (for example, see Japanese Laid-Open Patent Application No. 2003-209468).
Furthermore, in another exemplary DPLL circuit according to a related art case, there is provided a sequential loop filter having p (p where is an integer no less than 2) steps (hereinafter referred to as “p step sequential loop filter”) that integrates with different phases, a multi-phase clock generating circuit that provides p phase clock signals of different phases to the p step sequential loop filter, an adder that adds p integration signals output from the p step sequential loop filter and provides the signals to a variable divider, and a selecting circuit that selects an optimum clock signal from the multi-phase clock signals and outputs the selected signal (for example, see Japanese Laid-Open Patent Application No. 8-274628).
Furthermore, in an exemplary DPLL filter according to a related art case, there is provided a counter that counts the phase difference between input signals and output signals and outputs the counted value and an integrator that integrates the counted value with a predetermined value as a slope in the period of the clock signals and outputs an overflow (size error) signal whenever an overflow (size error) occurs (For example, see Japanese Laid-Open Patent Application No. 63-155824).
However, with the above-described DPLL circuit, the clock signals for operations inside the DPLL circuit (operating clock signals) are required to be high frequency clock signals in a case of increasing the time resolution of the clock signals output from the DPLL circuit. That is, since the recording speed and reproducing speed of CD drives and DVD drives have remarkably increased in recent years, there is a need to significantly increase the frequency of the operating clock signals inside the DPLL circuit. When the frequency of the operating clock signals is increased to such an extent, the operating frequency of the circuit exceeds its limit and causes the DPLL circuit to be inoperative.
Furthermore, although the above-described DPLL circuit may be provided with a VCO which outputs clock signals having high time resolution by using a digital circuit operating at a relatively low frequency, such a DPLL circuit requires a frequency bandwidth controlling part for the next step such as an analog PLL circuit or an analog band pass filter. However, with such a configuration, the DPLL circuit cannot be a fully digitized circuit. Therefore, in a case of attempting to integrate such a DPLL circuit into a single IC (integrated chip), the IC becomes a mixed signal IC having mixed analog and digital circuits. This complicates the manufacturing process and increases manufacturing cost.
Furthermore, with the above-described DPLL circuit, it is necessary to operate complicated logic circuits (e.g. sequential loop filter, variable divider) each with multi-phase clocks having different phase differences. It is therefore difficult to use the synchronous design methods used for digital circuits. Furthermore, the above-described DPLL circuit is basically configured to add one pulse when a phase is early and to subtract one pulse when a phase is delayed in accordance with the detection result of the phase difference between input signals and output signals. Therefore, with the above-described DPLL circuit, it is difficult to freely change characteristics (settings) such as response characteristics or loop bandwidth. As a result, designing the DPLL circuit becomes difficult.